module enqueueUpdateMuxer4 (
    input wire clk,
    input wire rst,
    input wire enqueue_update_en_1,
    input wire [5:0] enqueue_update_priority_1,
    input wire [7:0] is_first_tail_1,
    input wire [9:0] enqueue_tail_old_1,
    input wire [15:0] enqueue_tail_new_1,
    input wire enqueue_update_en_2,
    input wire [5:0] enqueue_update_priority_2,
    input wire [7:0] is_first_tail_2,
    input wire [9:0] enqueue_tail_old_2,
    input wire [15:0] enqueue_tail_new_2,
    input wire enqueue_update_en_3,
    input wire [5:0] enqueue_update_priority_3,
    input wire [7:0] is_first_tail_3,
    input wire [9:0] enqueue_tail_old_3,
    input wire [15:0] enqueue_tail_new_3,
    input wire enqueue_update_en_4,
    input wire [5:0] enqueue_update_priority_4,
    input wire [7:0] is_first_tail_4,
    input wire [9:0] enqueue_tail_old_4,
    input wire [15:0] enqueue_tail_new_4,
    output reg enqueue_update_en_out,
    output reg [5:0] enqueue_update_priority_out,
    output reg [7:0] is_first_tail_out,
    output reg [9:0] enqueue_tail_old_out,
    output reg [15:0] enqueue_tail_new_out
);
    wire [3:0] enqueue_arbitration;

    always @(posedge clk) begin
        //将输出信号进行复位
        if (rst) begin
            enqueue_update_en_out <= 1'b0;
            enqueue_update_priority_out <= 0;
        end

        if (enqueue_arbitration == 4'b0001) begin
            enqueue_update_en_out <= 1'b1;
            enqueue_update_priority_out <= enqueue_update_priority_1;
            is_first_tail_out <= is_first_tail_1;
            enqueue_tail_old_out <= enqueue_tail_old_1;
            enqueue_tail_new_out <= enqueue_tail_new_1;
        end

        if (enqueue_arbitration == 4'b0010) begin
            enqueue_update_en_out <= 1'b1;
            enqueue_update_priority_out <= enqueue_update_priority_2;
            is_first_tail_out <= is_first_tail_2;
            enqueue_tail_old_out <= enqueue_tail_old_2;
            enqueue_tail_new_out <= enqueue_tail_new_2;
        end

        if (enqueue_arbitration == 4'b0100) begin
            enqueue_update_en_out <= 1'b1;
            enqueue_update_priority_out <= enqueue_update_priority_3;
            is_first_tail_out <= is_first_tail_3;
            enqueue_tail_old_out <= enqueue_tail_old_3;
            enqueue_tail_new_out <= enqueue_tail_new_3;
        end

        if (enqueue_arbitration == 4'b1000) begin
            enqueue_update_en_out <= 1'b1;
            enqueue_update_priority_out <= enqueue_update_priority_4;
            is_first_tail_out <= is_first_tail_4;
            enqueue_tail_old_out <= enqueue_tail_old_4;
            enqueue_tail_new_out <= enqueue_tail_new_4;
        end

        if (enqueue_arbitration == 4'b0000) begin
            enqueue_update_en_out <= 1'b0;
        end
    end

    enqueueUpdateArbiter4 arb(.enqueue_update_en_1(enqueue_update_en_1), .enqueue_update_priority_1(enqueue_update_priority_1), 
                            .enqueue_update_en_2(enqueue_update_en_2), .enqueue_update_priority_2(enqueue_update_priority_2), 
                            .enqueue_update_en_3(enqueue_update_en_3), .enqueue_update_priority_3(enqueue_update_priority_3),
                            .enqueue_update_en_4(enqueue_update_en_4), .enqueue_update_priority_4(enqueue_update_priority_4), .enqueue_arbitration(enqueue_arbitration));
endmodule